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LTM4600HV
APPLICATIO S I FOR ATIO
In the application where the light load ef?ciency is im-
portant, tying the FCB pin above 0.6V threshold enables
discontinuous operation where the bottom MOSFET turns
off when inductor current reverses. Therefore, the conduc-
tion loss is minimized and light load ef?ciency is improved.
The penalty is that the controller may skip cycle and the
output voltage ripple increases at light load.
Paralleling Operation with Load Sharing
Two or more LTM4600HV modules can be paralleled to
provide higher than 10A output current. Figure 7 shows
the necessary interconnection between two paralleled
modules. The OPTI-LOOP? current mode control en-
sures good current sharing among modules to balance
the thermal stress. The new feedback equation for two or
more LTM4600HVs in parallel is:
explanation of the analysis for the thermal models, and the
derating curves. Tables 3 and 4 provide a summary of the
equivalent θ JA for the noted conditions. These equivalent
θ JA parameters are correlated to the measure values, and
improved with air-?ow. The case temperature is maintained
at 100°C or below for the derating curves. This allows for
4W maximum power dissipation in the total module with
top and bottom heatsinking, and 2W power dissipation
through the top of the module with an approximate θ JC
between 6°C/W to 9°C/W. This equates to a total of 124°C
at the junction of the device.
Safety Considerations
The LTM4600HV modules do not provide isolation from
V IN to V OUT . There is no internal fuse. If required, a slow
blow fuse with a rating twice the maximum input current
+ R SET
V OUT = 0 . 6 V ?
100k
N
R SET
should be provided to protect each unit from catastrophic
failure.
Layout Checklist/Example
where N is the number of LTM4600HVs in parallel.
The high integration of the LTM4600HV makes the PCB
board layout very simple and easy. However, to optimize
V IN
V IN
LTM4600HV
V OUT
V OUT
(20A MAX )
its electrical and thermal performance, some layout con-
siderations are still necessary.
PGND COMP V OSET SGND
R SET
? Use large PCB copper areas for high current path, in-
cluding V IN , PGND and V OUT . It helps to minimize the
PCB conduction loss and thermal stress
V IN
PGND
COMP V OSET SGND
LTM4600HV V OUT
4600hv F07
? Place high frequency ceramic input and output capaci-
tors next to the V IN , PGND and V OUT pins to minimize
high frequency noise
Figure 7. Parallel Two μModules with Load Sharing
Thermal Considerations and Output Current Derating
The power loss curves in Figures 8 and 15 can be used
in coordination with the load current derating curves in
Figures 9 to 14, and Figures 16 to 19 for calculating an
approximate θ JA for the module with various heatsink-
ing methods. Thermal models are derived from several
temperature measurements at the bench, and thermal
modeling analysis. Application Note 103 provides a detailed
OPTI-LOOP is a trademark of Linear Technology Corporation.
? Place a dedicated power ground layer underneath
the unit
? To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers
? Do not put vias directly on pad unless they are capped.
? Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit
Figure 20 gives a good example of the recommended
layout.
4600hvfc
14
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